Advances in high-density integration of resistive memory for microelectronics

(1) Typical IV characteristics of selectors with high uniformity and high selectivity. (2) IV characteristics of 1RRRAM and integrated gate 1S1R architecture. (3) Comparison of performance parameters of various types of gating devices.

Recently, the team of Liu Ming of the Key Laboratory of Microelectronic Devices and Integrated Technology of the Institute of Microelectronics of the Chinese Academy of Sciences has made new progress in the high-density integration of resistive random access memory (RRAM), and has proposed a method that is fully compatible with CMOS technology and has high homogeneity. High-performance gated devices provide solutions for high-density, three-dimensional integration of resistive memory on both ends. Fully BEOL Compatible TaOx-based Selector with High Uniformity and Robust Performance (Corresponding author: Lu Hang Ping, Liu Ming) The study results based on receiving the 2016 IEEE International Electron Devices Meeting (IEDM), the first author Luo Qing in the General Assembly for Report.

Leakage currents in cross arrays are a major obstacle to high-density memory integration. In the 1T1R structure, the transistor acts as a gating tube to isolate the bypass leakage, but the transistor is not suitable for 3D stacking. Therefore, the development of a gating device with high uniformity, high selectivity, high current density, and three-dimensional stacking is the key to achieving three-dimensional integration of RRAM. It is difficult for existing gate devices to satisfy the above requirements at the same time. In response to this problem, Liu Ming's team proposed the idea of ​​using a trapezoidal band structure to construct a gate tube device, and developed a gate device with high uniformity, high selectivity and current density, and its leakage current < 10 pA, non-linear ratio >50000, on-state current density >1 MA/cm2 and ultra-high durability (>1010).

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